(China (Mainland))
Product Summary
The CY62147VLL-70BAIT is a high-performance CMOS static RAM organized as 256K words by 16 bits. The device features advanced circuit design to provide ultra-low active current. The CY62147VLL-70BAIT also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The CY62147VLL-70BAIT can also be put into standby mode when deselected (CE HIGH) or when CE is LOW and both BLE and BHE are HIGH. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW.
Parametrics
CY62147VLL-70BAIT absolute maximum ratings: (1)Storage Temperature:–65℃ to +150℃; (2)Ambient Temperature with Power Applied:–55℃ to +125℃; (3)Supply Voltage to Ground Potential:–0.5V to +4.6V; (4)DC Voltage Applied to Outputs in High-Z State:–0.5V to VCC + 0.5V; (5)DC Input Voltage:–0.5V to VCC + 0.5V; (6)Output Current into Outputs (LOW):20 mA; (7)Static Discharge Voltage:> 2001V(per MIL-STD-883, Method 3015); (8)Latch-up Current:> 200 mA.
Features
CY62147VLL-70BAIT features: (1)Wide voltage range: 2.7V to 3.6V; (2)Ultra-low active, standby power; (3)Easy memory expansion with CE and OE features; (4)TTL-compatible inputs and outputs; (5)Automatic power-down when deselected; (6)CMOS for optimum speed/power; (7)Package available in a standard 44-pin TSOP Type II (forward pinout) package.
Diagrams
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 CY62126BV |
Other |
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Data Sheet |
Negotiable |
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CY62126DV30 |
Other |
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Data Sheet |
Negotiable |
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CY62126DV30L-55BVXE |
Cypress Semiconductor |
SRAM SLO 3.0V SUPER LO PWR 64K X 16 SRAM |
Data Sheet |
Negotiable |
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CY62126DV30L-55BVXET |
Cypress Semiconductor |
SRAM SLO 3.0V SUPER LO PWR 64K X 16 SRAM |
Data Sheet |
Negotiable |
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CY62126DV30L-55ZSXE |
Cypress Semiconductor |
SRAM SLO 3.0V SUPER LO PWR 64K X 16 SRAM |
Data Sheet |
Negotiable |
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CY62126DV30L-55ZSXET |
Cypress Semiconductor |
SRAM SLO 3.0V SUPER LO PWR 64K X 16 SRAM |
Data Sheet |
Negotiable |
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