EP2C35F672C7

Product Summary

The EP2C35F672C7 is a FPGA extending the low-cost FPGA density range to 68,416 logic elements (LEs) and providing up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. The EP2C35F672C7 is manufactured on 300-mm wafers using TSMC’s 90-nm low-k dielectric process to ensure rapid availability and low cost. By minimizing silicon area, the EP2C35F672C7 can support complex digital systems on a single chip at a cost that rivals that of ASICs. Unlike other FPGA vendors who compromise power consumption and performance for low-cost, Altera’s latest generation of low-cost FPGAs —Cyclone II FPGAs, offer 60 percent higher performance and half the power consumption of competing 90-nm FPGAs. The low cost and optimized feature set of the EP2C35F672C7 make it ideal solutions for a wide array of automotive, consumer, communications, video processing, test and measurement, and other end-market solutions.

Parametrics

EP2C35F672C7 absolute maximum ratings: (1)VCCINT, Supply voltage With respect to ground: –0.5 to 1.8 V; (2)VCCIO, Output supply voltage: –0.5 to 4.6 V; (3)VIN, DC input voltage: –0.5 to 4.6 V; (4)IOUT, DC output current, per pin: –25 to 40 mA; (5)TSTG, Storage temperature No bias: –65 to 150℃; (6)TJ, Junction temperature BGA packages under bias: 125℃.

Features

EP2C35F672C7 features: (1)M4K embedded memory blocks; (2)Up to 1.1 Mbits of RAM available without reducing available logic; (3)4,096 memory bits per block (4,608 bits per block including 512 parity bits); (4)Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36; (5)True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes; (6)Byte enables for data input masking during writes; (7)Up to 260-MHz operation; (8)Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance; (9)Optional input and output registers.

Diagrams