FWIXP422BB

Product Summary

The FWIXP422BB is a Product Line of Network Processor and IXC1100 Control Plane Processor. It is compliant with the ARM Version 5TE instruction-set architecture (ISA). The FWIXP422BB is designed with Intel 0.18-μ production semiconductor process technology. This process technology-along with the compactness of the Intel XScale core, the ability to simultaneously process up to three integrated network processing engines (NPEs), and numerous dedicated-function peripheral interfaces-enables the FWIXP422BB to operates over a wide range of low-cost networking applications, with industry-leading performance.

Parametrics

FWIXP422BB absolute maximum ratings: (1)Ambient Air Temperature (Extended): -40℃ to 85℃; (2)Ambient Air Temperature (Commercial): 0℃ to 70℃; (3)Supply Voltage Core: -0.3 V to 2.1V; (4)Supply Voltage I/O: -0.3 V to 3.6V; (5)Supply Voltage Oscillator (VCCOSC): -0.3 V to 2.1V; (6)Supply Voltage Oscillator (VCCOSCP): -0.3 V to 3.6V; (7)Supply Voltage PLL (VCCPLL1): -0.3 V to 2.1V; (8)Supply Voltage PLL (VCCPLL2): -0.3 V to 2.1V; (9)Voltage On Any I/O Ball: -0.3 V to 3.6V; (10)Storage Temperature: -55℃ to 125℃.

Features

FWIXP422BB features: (1)High-performance processor based on Intel XScale Microarchitecture; (2)Seven/eight-stage Intel Super-Pipelined RISC Technology; (3)Management unit; (4)32-entry, data memory management unit; (5)32-entry, instruction memory management unit; (6)32-Kbyte, 32-way, set associative instruction cache; (7)32-Kbyte, 32-way, set associative data cache; (8)2-Kbyte, two-way, set associative mini-data cache; (9)128-entry, branch target buffer; (10)Eight-entry write buffer; (11)Four-entry fill and pend buffers; (12)PCI Local Bus Specification, Rev. 2.2 compatible; (13)PCI arbiter supporting up to four external PCI devices (four REQ/GNT pairs); (14)Host/option capable; (15)Master/target capable; (16)Two DMA channels; (17)32-bit data; (18)13-bit address; (19)133MHz; (20)Up to eight open pages simultaneously maintained; (21)Programmable auto-refresh; (22)Programmable CAS/data delay; (23)Support for 8 MB, minimum, up to 256 MB maximum.

Diagrams