MPC8250AVRIHBB

Product Summary

The MPC8250AVRIHBB is a communications processor. It is available in two packages: the standard ZU package (480 TBGA) and an alternate VR package (516 PBGA).

Parametrics

MPC8250AVRIHBB absolute maximum ratings: (1)Core supply voltage:-0.3V to 2.5V; (2)PLL supply voltage:-0.3V to 2.5V; (3)I/O supply voltage:-0.3V to 4.0V; (4)Input voltage:GND(-0.3)V to 3.6V; (5)Junction temperature:120℃; (6)Storage temperature rang:-55℃ to +150℃.

Features

MPC8250AVRIHBB features: (1)Footprint-compatible with the MPC8260; (2)Dual-issue integer core; (3)A core version of the EC603e microprocessor; (4)System core microprocessor supporting frequencies of 150MHz to 200MHz; (5)PowerPC architecture-compliant memory management unit (MMU); (6)Common on-chip processor (COP) test interface; (7)High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at 200 MHz); (8)Supports bus snooping for data cache coherency; (9)Floating-point unit (FPU); (10)Separate power supply for internal logic (1.8 V) and for I/O(3.3V) ; (11)Separate PLLs for G2 core and for the CPM; (12)Bus supports multiple master designs; (13)Supports single- and four-beat burst transfers ; (14)64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller; (15)Supports data parity or ECC and address parity; (16)Programmable host bridge and agent; (17)32-bit data bus, 66 MHz, 3.3 V; (18)Synchronous and asynchronous 60x and PCI clock modes; (19)All internal address space available to external PCI host; (20)DMA for memory block transfers; (21)PCI-to-60x address remapping; (22)Clock synthesizer; (23)Reset controller; (24)Real-time clock (RTC) register; (25)Periodic interrupt timer; (26)Hardware bus monitor and software watchdog timer; (27)IEEE 1149.1 JTAG test access port; (28)Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller; (29)Serial DMA channels for receive and transmit on all serial channels; (30)Parallel I/O registers with open-drain and interrupt capability; (31)Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers.

Diagrams