EP1S10F672C7N

Product Summary

The EP1S10F672C7N is an FPGA. It is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. The EP1S10F672C7N offers up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit × 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. The EP1S10F672C7N supports various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs).

Parametrics

EP1S10F672C7N absolute maximum ratings: (1)Supply voltage:VCCINT:–0.5V to 2.4V, VCCIP:–0.5V to 4.6V; (2)DC input voltage:–0.5V to 4.6V; (3)DC output current, per pin:–25mA to 40mA; (4)Storage temperature No bias:–65℃ to 150℃; (5)Junction temperature BGA packages under bias:135℃.

Features

EP1S10F672C7N features: (1)10,570 to 79,040 LEs; (2)Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources; (3)TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO)buffers; (4)High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters; (5)Up to 16 global clocks with 22 clocking resources per device region; (6)Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switch-over, real-time PLL reconfiguration, and advanced multiplication and phase shifting; (7)Support for numerous single-ended and differential I/O standards; (8)High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (Mbps); (9)Support for high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4; (10)Differential on-chip termination support for LVDS; (11)Support for remote configuration updates.

Diagrams