Product Summary

The TDA10046HT/C1 is a Single-chip DVB-T channel decoder. The TDA10046HT/C1 performs all DVB-T channel decoding functions from IF input to transport stream output, using an internal DSP core for synchronization and control. Thanks to its sharp adjacent channel digital ilter, this single-chip receiver achieves excellent performance with low cost tuners (one SAW only). The TDA10046HT/C1 requires only a low cost crystal oscillator (4 MHz) as a clock source, which can be shared with the tuner. After sampling of the 1st or 2nd IF by a 10-bit ADC, the signal is converted to baseband and passes through the FFT demodulator. Channel frequency response is then estimated and iltered in both time and frequency domains, and used to equalize the signal. A common phase error correction handles tuner phase noise. The applications of the TDA10046HT/C1 include Integrated Digital TV (iDTV), Set-Top-Boxes (STB), and Personal Video Recorder (PVR) with DVB-T reception, Digital TV PCI card for Personal Computers.

Features

TDA10046HT/C1 features: (1)2K and 8K COFDM demodulator, fully ETS 300-744 compliant; (2)TPS and Cell Identiier2I C-bus readable; (3)2nd or 1st IF analog input; (4)On chip 10-bit ADC and PLL; (5)Single or dual AGC loop (with programmable takeover point); (6)Adjacent channel digital iltering (only one external SAW ilter is required); (7)Automatic frequency offset detection (±1, 2 or 3 standard offsets); (8)Dynamic FFT window positioning, and adaptive echo equalization; (9)Consolidated algorithm for impulsive noise reduction; (10)DSP based synchronization enables on the ly irmware upgrades; (11)No extra-host software required; (12)Fast UHF/VHF band scanning; (13)Simultaneous tri-state parallel and serial Transport Stream interfaces; (14)I2C-bus interface; (15)5V tolerant I/O pins; (16)Low power consumption (450mW); (17)TQFP64 package, CMOS 0.18μm technology.

Diagrams

TDA10046HT/C1 block diagram

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